1. Field of the Invention
Embodiments of the present invention relate to semiconductor packages.
2. Description of the Related Arts
According to the development of a semiconductor technique and the users' demand, miniaturization of the size of and lightening of the weight of electronic devices have been implemented. Thus, a multi-chip packaging technique for implementing the same kind or different kinds of semiconductor chips as a single unit package has emerged. The multi-chip packaging method is effective to reduce a package size or weight and to mount semiconductor chips compared to a packaging method for implementing respective semiconductor chips as packages. In particular, the multi-chip packaging is frequently applied to portable communication terminals and the like for which miniaturization and lightening are required.
Among various types of multi-chip packaging, a stack type of multi-chip packaging in which two or more packages are stacked on each other is called Package on Package (hereinafter referred to as “PoP”). According to the development of a semiconductor package technique, and the improvement of high-capacity, thinning and miniaturization of the semiconductor package, the number of laminated chips has been increasing.
In a conventional package on package method, two packages are connected by a solder ball print and reflow process, or a lower package is first molded, and a molded portion is subjected to a laser drilling process so that vias are formed in a PoP pad of the lower package (i.e., a Through Molded Via Method), and a solder ball is printed in the vias, thereby connecting the lower package to an upper package, to which a memory die is mounted, using the reflow process.
In order to implement the high-integration and high performance of package on package products, the number of mounted dies has been increasing, or an attempt to mount a passive element has been performed. For this purpose, it has been required to widen a distance between packages.
However, the semiconductor package according to the conventional art is problematic in that cracks in solder balls or destroy occurs when sizes or heights of the solder balls are increased for widening a distance between semiconductor packages.